求verilog编写下面文件的测试信号

module sell(one_dollar,half_dollar,
collect,half_out,dispense,reset,clk);
parameter idle=0,one=2,half=1,two=3,three=4;
//idle,one,half,two,three为中间状态变量，代表投入币值的几种情况
input one_dollar,half_dollar,reset,clk;
output collect,half_out,dispense;
reg collect,half_out,dispense;
reg[2:0] D;
always @(posedge clk)
begin
if(reset)
begin
dispense=0; collect=0;
half_out=0; D=idle;
end
case(D)
idle:
if(half_dollar) D=half;
else if(one_dollar)
D=one;
half:
if(half_dollar) D; =one
else if(one_dollar)
D=two;
one:
if(half_dollar) D=two;
else if(one_dollar)
D=three;
two:
if(half_dollar) D=three;
else if(one_dollar)
begin
dispense=1; //售出饮料
collect=1; D=idle;
end
three:
if(half_dollar)
begin
dispense=1; //售出饮料
collect=1; D=idle;
end
else if(one_dollar)
begin
dispense=1; //售出饮料
collect=1;
half_out=1; D=idle;
end
endcase
end
endmodule

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:19:44 06/21/2010
// Design Name: sell
// Module Name: D:/Xilinx/11.1/myproject/baidu/test.v
// Project Name: baidu
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sell
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module test;

// Inputs
reg one_dollar;
reg half_dollar;
reg reset;
reg clk;

// Outputs
wire collect;
wire half_out;
wire dispense;
reg k;

// Instantiate the Unit Under Test (UUT)
sell uut (
.one_dollar(one_dollar),
.half_dollar(half_dollar),
.collect(collect),
.half_out(half_out),
.dispense(dispense),
.reset(reset),
.clk(clk)
);

initial begin
// Initialize Inputs
one_dollar = 0;
half_dollar = 0;
reset = 0;
clk = 0;
k=0;
// Wait 100 ns for global reset to finish
#100;
reset=1;
// Add stimulus here

end
always #5 clk=~clk;
always@(posedge clk)
begin
if(reset==0)
begin
one_dollar = 0;
half_dollar = 0;
end
else
begin
if(k==0)
begin
one_dollar=1;
half_dollar=0;
end
else
begin
half_dollar=1;
one_dollar=0;
end
if(collect==1)
begin
k=~k;
end

end
end
endmodule

程序的语法没有问题，但实际上这程序根本无法工作。你把问题简化的太简单了

计一个下降沿触发，带低电平置位的触发器，编写测试文件并 k肯定还好

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