verilog数字时钟里头一个赋值错误 求改正

应该是某个变量在赋值时出了问题(多次赋值等等)= =本人新手, 找了好久没找出来啥问题= =求指出, 谢谢!

报错信息:

ERROR:Xst:528 - Multi-source in Unit <main> on signal <Mcount_count_cy<0>>; this signal is connected to multiple drivers.
Drivers are:
Output signal of FD instance <count_0>
Signal <count<0>> in Unit <main> is assigned to GND

附:部分源码

module main(clk, rst, add, set, an, seg, dp);
input clk;
input rst;
input set;
input [3:0] add;
output reg [3:0] an;
output reg [6:0] seg;
output reg dp;

//reg [3:0] reg_add1;
//reg [3:0] reg_add2;
//reg [3:0] reg_add;
//reg [19:0] reg_count;

reg clk4000; //4000Hz
reg clk1; //1Hz
reg clk4;
reg [15:0] cnt1;
reg [25:0] cnt2;
reg [25:0] cnt3;
reg [1:0] count;
reg [1:0] count1;
reg [3:0] disp;
reg [3:0] second1;
reg [3:0] second0;
reg [3:0] minute1;
reg [3:0] minute0;
always @(posedge clk4 or posedge set) //计时
begin

if(second0>4'b1001) second0<=4'b0;
if(second1>4'b0101) second1<=4'b0;
if(minute0>4'b1001) minute0<=4'b0;
if(minute1>4'b0101) minute1<=4'b0;

if(set)
begin
if(add[0])
begin
if(second0<4'b1001) second0<=second0+4'b1;
else second0<=0;
end
else
if(add[1])
begin
if(second1<4'b0101) second1<=second1+4'b1;
else second1<=4'b0;
end
else
if(add[2])
begin
if(minute0<4'b1001) minute0<=minute0+4'b1;
else minute0<=4'b0;
end
else
if(add[3])
begin
if(minute1<4'b0101) minute1<=minute1+4'b1;
else minute1<=4'b0;
end

end
else

if(count1==2'b11)
begin
count<=0;

if (second0<4'b1001) second0<=second0+4'b1;
else
begin
second0<=4'b0;
if (second1<4'b0101) second1<=second1+4'b1;
else
begin
second1<=4'b0;
if (minute0<4'b1001) minute0<=minute0+4'b1;
else
begin
minute0<=4'b0;
if (minute1<4'b0101) minute1<=minute1+4'b1;
else minute1<=4'b0;
end
end
end
end
else
count1<=count1+2'b1;

end
还有一个将二进制码转换为7段数码管显示的模块, 确定没有问题,同时因为字数限制,不再贴了= =谢谢各位!

Mcount_count_cy<0> 这个信号有多个驱动源，有可能在两个always块中操作。

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