Adiabatic logic utilizes AC voltage supplies (power-clocks)
to recycle the energy of circuits, which is an attractive low-
power approach. Several adiabatic logic families and their
applications have been reported for reducing dynamic energy
dissipations [8, 9]. Similar to power-gating techniques of
conventional CMOS circuits, power-gating schemes for
adiabatic circuits have been proposed and achieved
considerable energy savings [10, 11]. However, the previously
reported power-gating adiabatic circuits are mostly
investigated for reducing their dynamic energy dissipations
during idle periods [10, 11].
This paper focuses on leakage reduction of Improved CAL
(Clocked Adiabatic Logic) circuits using power-gating
schemes in scaled CMOS processes. Taken as an example,
energy dissipations of an 8-bit full adder based on improved
CAL circuits with power-gating schemes are investigated in
different processes, frequencies and active ratios. All circuits
are verified using HSPICE, and BSIM4 model [12] is adopted
to reflect the leakage current. HSPICE simulations show that
the 8-bit adiabatic full adder with power-gating schemes
shows significant improvement in terms of leakage
consumptions in deep submicron process.
毕业设计要文献翻译,感谢各位朋友帮忙,小弟英语不行,非常感谢了
答案:2 悬赏:0 手机版
解决时间 2021-05-10 14:10
- 提问者网友:眉目添风霜
- 2021-05-10 09:39
最佳答案
- 五星知识达人网友:酒醒三更
- 2021-05-10 10:02
现在很多网站都能翻译啊,反正老师也不看,看他也看不懂!呵呵..什么谷歌 有道之类的都行
全部回答
- 1楼网友:妄饮晩冬酒
- 2021-05-10 10:34
谷歌翻译撒,简单快捷。
我要举报
如以上回答内容为低俗、色情、不良、暴力、侵权、涉及违法等信息,可以点下面链接进行举报!
点此我要举报以上问答信息
大家都在看
推荐资讯