FPGA设计移相触发脉冲

FPGA设计移相触发脉冲

你的思路基本没动，加了些控制，code如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity PhaseShift3 is
Generic (PH30:natural range 0 to 1000000:=83333; ---30°
PH60:natural range 0 to 1000000:=166666; ---60°
PH90:natural range 0 to 1000000:=249999; ---90°
PH180:natural range 0 to 1000000:=499999); ---180°
port(
clkin: in std_logic;
pin : in std_logic;
pout : out std_logic );
end PhaseShift3;

architecture behave of PhaseShift3 is
signal cnten :std_logic:='0';
signal reset :std_logic:='1';
begin

process(pin, clkin,reset,cnten)
variable countf: natural range 0 to 9000;
variable count0,count: natural range 0 to 1000000;
begin
if (reset='0') then
cnten<='0';
elsif (pin'event and pin='1') then
cnten<='1';
end if;
if (pin'event and pin='1') then
countf:=countf+1;
if countf=8999 then
countf:=0;
end if;
end if;
case countf is ---------每60秒 count0 轮询一次；
when 2999=>count0<=PH30;
when 5999=>count0<=PH60;
when 8999=>count0<=PH90;
when others=>null;
end case;

if (clkin'event and clkin='1') then
if (cnten='1') then
count:=count+1;
if count=count0 then -----在要求相位时置1；
pout<='1';
end if;
if count=PH180 then -----在T/2处置0；
pout<='0';
count:=0;
reset<='0';
end if;
else
count:=count+1;
if count=10 then
reset<='1';
count:=0;
end if;
end if;
end if;
end process;

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