用74LS76怎么实现三进制计数？

用74LS76怎么实现三进制计数？

我写的是否是你想要的。
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity cnt_3or7 is
port (
clk: in STD_LOGIC;
k: in STD_LOGIC;
q: out STD_LOGIC_VECTOR (2 downto 0)
);
end cnt_3or7;

architecture cnt_3or7_arch of cnt_3or7 is
signal en:integer range 0 to 1;
signal qq:std_logic_vector(2 downto 0);
begin
process(clk)
variable n:integer range 0 to 2;
begin
if clk'event and clk='1' then
if n=2 then en<=1;
else
n:=n+1;en<=0;
end if;
end if;
end process;

process(clk,k,en)
begin
if en=1 then
if clk'event and clk='1' then
if k='1' then
if qq="111" then
qq<="000";
else
qq<=qq+'1';
end if;
else
if qq="011" then
qq<="000";
else
qq<=qq+'1' ;
end if;
end if;
end if;
end if;
end process;

process(qq)
begin
q<=qq;
end process;

end cnt_3or7_arch;

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