vhdl case语句纠错， 用 VHDL 设计一个数据转换器 ，功能是将一位 16 进制码转换为两位 10 进制码。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
d,h,l都是向量，d的输入是模16减法计数器，程序如下：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity gdf is
Port ( d : in signed(3 downto 0);
H : out signed(3 downto 0);
L : out signed(3 downto 0));
end gdf;

architecture Behavioral of gdf is

begin
process(d)
begin
case d is
when "1010"to"1111" => H<="0001",L<=d-"1010";
when "0000"to"1001" => H<="0000",L<=d;
end case;
end process;
end Behavioral;
有好多错，HDLParsers:800 - "D:/2016/text_6/gdf.vhd" Line 45. Type of H is
incompatible with type of <=.
ERROR:HDLParsers:825 - "D:/2016/text_6/gdf.vhd" Line 45. Range declaration does
not match type definition.
ERROR:HDLParsers:800 - "D:/2016/text_6/gdf.vhd" Line 46. Type of H is
incompatible with type of <=.
ERROR:HDLParsers:825 - "D:/2016/text_6/gdf.vhd" Line 46. Range declaration does
not match type definition.

when子句中出现了","是不对的：
when "1010" to "1111" => H<="0001",L<=d-"1010";
when "0000" to "1001" => H<="0000",L<=d;
试试将","改成";"：
when "1010" to "1111" => H<="0001"; L<=d-"1010";
when "0000" to "1001" => H<="0000"; L<=d;

我用quartus ii9.0帮你综合了一下，没报错啊，只是warning多了点，证明你存在功能性错误而不是语法错误。 建议你的clk用边沿触发，即rising_edge(clk),然后再判断0或1。 还有最后把sl1,sh1,ml1,mh1,hl1,hh1加进process的敏感电平列表内。 虽然warning可以去不管它，但太多的warning会使系统不稳定或跑飞。 我补充一下：你是不是忘了建个project?

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