求EDA实习课题

求EDA实习课题

电子钟的 要不 要了 就下面的程序：0.01秒表模块
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity s99 is
port( En : in std_logic;
clk : in std_logic;
count: out std_logic;
Low : out std_logic_vector(3 downto 0);
High : out std_logic_vector(3 downto 0);
str : in std_logic; kz : in std_logic); end s99;
architecture s99_clock of s99 is
signal sa,sb :std_logic_vector(3 downto 0);
signal ssa :std_logic;
begin
process(clk,En,str,sa,sb)
begin
if kz='1' then sa<="0000";sb<="0000"; else
if str='0' then
if En='0' then
if (clk'event and clk='1') then
if sa=8 and sb=9 then ssa<='1'; else
if sa=1 and sb=0 then ssa<='0'; end if;
end if;
if sa=9 then
sa<="0000";
if sb=9 then sb<="0000";
else sb<=sb+1;
end if;
else sa<=sa+1; end if; end if; end if;
else sa<="0000"; sb<="0000";
end if;
end if;
if sb=9 and sa=9 and ssa='1' and En='0' and str='0' then
count<='1';
else count<='0';
end if;
end process;
Low<=sa;
High<=sb;
end s99_clock;

秒表模块
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ss60 is
port( En : in std_logic;

clk : in std_logic;
count: out std_logic;
Low : out std_logic_vector(3 downto 0);
High : out std_logic_vector(3 downto 0);
str : in std_logic);
end ss60;
architecture ss60_clock of ss60 is
signal sa,sb :std_logic_vector(3 downto 0);
signal ssa:std_logic;
begin
process(clk,En,str)
begin
if str='0' then
if En='0' then
if clk'event and clk='1' then
if sa=9 and sb=5 then ssa<='1'; else
if sa=1 and sb=0 then ssa<='0'; end if;
end if;
if sa=9 then sa<="0000";
if sb=5 then sb<="0000"; else
sb<=sb+1;
end if;
else
sa<=sa+1;
end if; end if; end if;
else sa<="0000"; sb<="0000";
end if;
Low<=sa; High<=sb;
if sb=0 and sa=0 and ssa='1' and En='0' and str='0' then
count<='1';
else count<='0';
end if;
end process;
end ss60_clock;
分表模块
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity m60 is
port( En : in std_logic;

clk : in std_logic;
count: out std_logic;
Low : out std_logic_vector(3 downto 0);
High : out std_logic_vector(3 downto 0);
str : in std_logic
);
end m60;
architecture m60_clock of m60 is
signal ma,mb :std_logic_vector(3 downto 0);
signal ssa :std_logic;
begin
process(clk,En,str)
begin
if str='0' then
if En='0' then
if clk'event and clk='1' then
if ma=9 and mb=5 then ssa<='1'; else
if ma=1 and mb=0 then ssa<='0'; end if;
end if;
if ma=9 then
ma<="0000";
if mb=5 then mb<="0000";
else
mb<=mb+1;
end if;
else
ma<=ma+1;
end if;
end if;
end if;
else ma<="0000"; mb<="0000";
end if;
Low<=ma;
High<=mb;
if mb=5 and ma=9 and ssa='1' and En='0' and str='0' then
count<='1';
else count<='0';
end if;
end process;
end m60_clock;

时模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity h24 is
port( clk :in std_logic;
En :in std_logic;
str:in std_logic;
High :out std_logic_vector(3 downto 0);
Low :out std_logic_vector(3 downto 0));
end h24;
architecture h24_clock of h24 is
signal ha:std_logic_vector(3 downto 0);
signal hb:std_logic_vector(3 downto 0);
begin
process(clk,En,str)
begin
if str='0' then
if En='0' then
if clk'event and clk='1' then
if(ha="0011" and hb="0010") then
ha<="0000";
hb<="0000";
else
if ha="1001" then
ha<="0000";
hb<=hb+'1';
else
ha<=ha+'1';
end if ;
end if;
end if;
end if;
else
ha<="0000";
hb<="0000";
end if;
Low<=ha;
High<=hb;
end process;
end h24_clock;

校时模块
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity js is
port(kz : in std_logic; -- 按键 选择 要调节的秒、分、时
t :in std_logic;
tm :in std_logic; -- 调节 按一下计数加1
cs: out std_logic; -- 秒 调节端口
cm: out std_logic; -- 分 调节端口
ch: out std_logic ); -- 时 调节端口
end js;
architecture js_clock of js is
signal aa:std_logic;
signal sl:std_logic_vector(1 downto 0);

begin
process(kz,t,tm)
begin

if kz'event and kz='1' then aa<=not aa; end if;
if aa='1' then

if t'event and t='1' then
if sl=2 then sl<="00";else sl<=sl+'1';
end if;
end if;
case sl is
when "00" => cs<=tm;cm<='0';ch<='0';
when "01"=> cm<=tm;cs<='0';ch<='0';
when "10"=> ch<=tm;cs<='0';cm<='0';
when others => cs<='0';cm<='0';ch<='0';
end case; else cs<='0';cm<='0';ch<='0';sl<="00";
end if;
end process ;
end js_clock;

延时模块
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity delay is
port(
en: in std_logic;
str: in std_logic;
clk: in std_logic;
en_out : out std_logic;
str_out : out std_logic;
en_o : out std_logic );
end delay;
architecture delay_clock of delay is

signal sa :std_logic:='0' ;
signal ss :std_logic:='0' ;
signal count :std_logic_vector(5downto 0) ;
begin
b1:process(str,clk)
begin
if clk'event and clk='1' then
if str='1' then
if count<31 then
count<=count+1; else count<=count;
end if;
if count=30 then str_out<='1';else str_out<='0'; end if;
else count<="000000" ;str_out<='0';
end if;
end if;
end process b1;
b2:process(en)
begin

if en'event and en='1' then ss<=not ss;end if;
end process b2;
b3:process(en)
begin
if str'event and str='1' then sa<=not sa;end if;
end process b3;
en_out<=ss;
en_o<=sa;
end delay_clock;

分频模块
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fp is
port( clk: in std_logic;
fp :out std_logic ; ff :out std_logic ); end fp ;
architecture fp_clock of fp is
signal aa:std_logic_vector(14 downto 0);
signal count:std_logic_vector(9 downto 0);
signal sse:std_logic;
signal bb:std_logic;
begin
b1:process(clk)
begin
if clk'event and clk='1' then
if count= "1010010110" then count<=(others =>'0'); sse<= '1';
else sse<='0';
count<=count+'1';--"1010001111" 655 662"1010010110"
end if; end if;
fp<=sse;
end process b1 ;
b2:process(sse)
begin
if sse'event and sse='1' then
if aa= "100011100010010" then aa<=(others =>'0'); bb<= '1'; else
bb<='0';-- "100011100010010" 18194
end if;
end if;
ff<=bb;
end process b2;
end fp_clock;

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