利用verilogHDL设计节日七个彩灯逐个亮，并循环闪烁。。。最好利用阻塞与非阻塞，麻烦你了

利用verilogHDL设计节日七个彩灯逐个亮，并循环闪烁。。。最好利用阻塞与非阻塞，麻烦你了

阻塞赋值
module led_top(resetb, clk, led)
input resetb;
input clk;
output [6:0] led;
reg [6:0] led, led_wire;
always @(negedge resetb, posedge clk)
if (~resetb)
led <= 7'h01;
else
led <= led_wire;
always @(led)
led_wire = {led[5:0], led[6]};
endmodule

推荐使用非阻塞赋值
module led_top(resetb, clk, led)
input resetb;
input clk;
output [6:0] led;
reg [6:0] led;
always @(negedge resetb, posedge clk)
if (~resetb)
led <= 7'h01;
else
led <= {led[5:0], led[6]};
endmodule追问module non_block(c,b,a,clk);
output c,b;
input clk,a;
reg c,b;
always@(posedge clk)
begin
b<=a;
c<=b;
end
endmodule

能仿照这个例子吗？我们老师要求。。根据这个例子。。追答module led_top(resetb, clk, led)
input resetb;
input clk;
output [6:0] led;
reg [6:0] led;
always @(negedge resetb, posedge clk)
if (~resetb)
led <= 7'h01;
else
begin
led[0] <= led[6];
led[1] <= led[0];
led[2] <= led[1];
led[3] <= led[2];
led[4] <= led[3];
led[5] <= led[4];
led[6] <= led[5];
end
endmodule来自：求助得到的回答

两个问题
1.分太低了
2.这个问题比较专业，去专门的电子论坛吧，这的人未必能行。。。。

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