verilog编程，在quartus2下编译报错
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解决时间 2021-02-17 20:15
- 提问者网友：無理詩人
- 2021-02-17 00:08
verilog编程，在quartus2下编译报错
最佳答案
- 五星知识达人网友：有你哪都是故乡
- 2021-02-17 00:24
改成这样就好了
always @(posedge clk or negedge rst)
if(!rst) cnt<=5'd0;
else if(load) cnt<=data;
else cnt<=cnt+5'd1;
学verilog语法看夏宇闻的《Verilog数字系统设计教程（第二版）》。
always @(posedge clk or negedge rst)
if(!rst) cnt<=5'd0;
else if(load) cnt<=data;
else cnt<=cnt+5'd1;
学verilog语法看夏宇闻的《Verilog数字系统设计教程（第二版）》。
全部回答
- 1楼网友：几近狂妄
- 2021-02-17 02:32
0.0
- 2楼网友：三千妖杀
- 2021-02-17 01:30
assign用于连续赋值Continuous Assignment，只能付给net类型，若将assign用在了过程块中（initial，always）,则此时是过程连续赋值 Procedural Continuous Assignment，此时，它只支持寄存器。 以下是外国教材：
9.1 Procedural Continuous Assignments
We studied procedural assignments in , Procedural Assignments. Procedural assignments assign a value to a register. The value stays in the register until another procedural assignment puts another value in that register. Procedural continuous assignments behave differently. They are procedural statements which allow values of expressions to be driven continuously onto registers or nets for limited periods of time. Procedural continuous assignments override existing assignments to a register or net. They provide an useful extension to the regular procedural assignment statement.
9.1.1 assign and deassign
The keywords assign and deassign are used to express the first type of procedural continuous assignment. The left-hand side of procedural continuous assignments can be only be a register or a concatenation of registers. It cannot be a part or bit select of a net or an array of registers. Procedural continuous assignments override the effect of regular procedural assignments. Procedural continuous assignments are normally used for controlled periods of time.
A simple example is the negative edge-triggered D-flipflop with asynchronous reset that we modeled in . In , we now model the same D_FF, using assign and deassign statements.
9.1 Procedural Continuous Assignments
We studied procedural assignments in , Procedural Assignments. Procedural assignments assign a value to a register. The value stays in the register until another procedural assignment puts another value in that register. Procedural continuous assignments behave differently. They are procedural statements which allow values of expressions to be driven continuously onto registers or nets for limited periods of time. Procedural continuous assignments override existing assignments to a register or net. They provide an useful extension to the regular procedural assignment statement.
9.1.1 assign and deassign
The keywords assign and deassign are used to express the first type of procedural continuous assignment. The left-hand side of procedural continuous assignments can be only be a register or a concatenation of registers. It cannot be a part or bit select of a net or an array of registers. Procedural continuous assignments override the effect of regular procedural assignments. Procedural continuous assignments are normally used for controlled periods of time.
A simple example is the negative edge-triggered D-flipflop with asynchronous reset that we modeled in . In , we now model the same D_FF, using assign and deassign statements.
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