求助VHDL分频器：晶振50MHz，计数时钟频率1hz，占空比75%。
答案:2 悬赏:40 手机版
解决时间 2021-02-23 10:37
- 提问者网友：ミ烙印ゝ
- 2021-02-22 14:44
求助VHDL分频器：晶振50MHz，计数时钟频率1hz，占空比75%。
最佳答案
- 五星知识达人网友：纵马山川剑自提
- 2021-02-22 15:55
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div is
generic(n:integer :=50000000);
port (clk:in std_logic;
q:out std_logic);
end div;
architecture behave of div is
signal count :integer range n-1 downto 0:=n-1;
begin
process(clk)
begin
if (clk'event and clk='1' and clk'last_value ='0') then
count<=count-1;
if count>=3*n/4 then
q<='0';
else
q<='1';
end if;
if count<=0 then
count<=n-1;
end if;
end if;
end process;
end behave;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div is
generic(n:integer :=50000000);
port (clk:in std_logic;
q:out std_logic);
end div;
architecture behave of div is
signal count :integer range n-1 downto 0:=n-1;
begin
process(clk)
begin
if (clk'event and clk='1' and clk'last_value ='0') then
count<=count-1;
if count>=3*n/4 then
q<='0';
else
q<='1';
end if;
if count<=0 then
count<=n-1;
end if;
end if;
end process;
end behave;
全部回答
- 1楼网友：山有枢
- 2021-02-22 16:05
我不知道，跟什么有关是啊
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