急用：EDA课设（MAX10.2）：计数器7段数码管控制接口设计（请高手帮忙）

要求：1.用设计一个共阴7段数码管控制接口，在硬件时钟电路的基础上，采用分频器，输出一个1S的时钟信号，在时钟信号的控制下，使6位数码管动态刷新显示0—F，其中为选信号为8-3编码器编码输出。
2.设计一个带使能输入，进位输出及同步清0的增1十进制计数器。
3.设计一个带使能输入及同步清0的六十进制同步加法计数器。
4.设计一个四位二进制可逆计数器

段译码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------Duan Decoder--------------
entity ddecoder is
port
(
a:in std_logic_vector(3 downto 0);
b:out std_logic_vector(6 downto 0)
);
end entity;
----------------------------------
architecture art of ddecoder is
begin
process(a)is
begin
case a is
when "0000"=>b<="1000000";
when "0001"=>b<="1111001";
when "0010"=>b<="0100100";
when "0011"=>b<="0110000";
when "0100"=>b<="0011001";
when "0101"=>b<="0010010";
when "0110"=>b<="0000010";
when "0111"=>b<="1111000";
when "1000"=>b<="0000000";
when "1001"=>b<="0010000";
when others=>b<="1000000";
end case;
end process;
end art;
位译码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------Wei Decoder--------------
entity wdecoder is
port
(
a:in std_logic_vector(2 downto 0);
b:out std_logic_vector(5 downto 0)
);
end entity;
----------------------------------
architecture art of wdecoder is
begin
process(a) is
begin
case a is
when "000"=>b<="000001";
when "001"=>b<="000010";
when "010"=>b<="000100";
when "011"=>b<="001000";
when "100"=>b<="010000";
when "101"=>b<="100000";
when others=>b<="000001";
end case;
end process;
end art;
位译码计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------Scan Counter-----------------
entity scancounter is
port
(
clk:in std_logic;
output:out std_logic_vector(2 downto 0)
);
end entity;
------------------------------------
architecture art of scancounter is
begin
process(clk)
variable outbuf:std_logic_vector(2 downto 0):="000";
begin
if clk'event and clk='1' then
outbuf:=outbuf+1;
if outbuf=6 then
outbuf:="000";
end if;
end if;
output<=outbuf;
end process;
end art;
60进制计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
----Minute and Second Counter----
entity cnt_60 is
port
(
clk,clr,en:in std_logic;
outen:out std_logic;
output:out std_logic_vector(7 downto 0)
);
end cnt_60;
---------------------------------
architecture art of cnt_60 is
signal olow,ohigh:std_logic_vector(3 downto 0):="0000";
--signal carry:std_logic;
begin
outen<='0' when olow=9 and ohigh=5 else '1';
output(7 downto 4)<=ohigh;
output(3 downto 0)<=olow;
process(clk,clr,en,olow,ohigh)
begin
if clr='0' then
olow<="0000";
ohigh<="0000";
elsif clk'event and clk='1' then
if en='1' then
if olow=9 then
olow<="0000";
if ohigh=5 then
ohigh<="0000";
else
ohigh<=ohigh+1;
end if;
else
olow<=olow+1;
end if;
end if;
end if;
output(7 downto 4)<=ohigh;
output(3 downto 0)<=olow;
end process;
end art;
其他的你自己仿照写吧

用设计一个共阴7段数码管控制接口，要求：在时钟信号的控制下，使6位数码管动态刷新显示0~F，其中位选信号为8-3编码器编码输出 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY disp_3 IS PORT ( CP : IN STD_LOGIC; SEG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); SEL : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); NUM : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END; ARCHITECTURE one OF disp_3 IS SIGNAL S : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL Q : STD_LOGIC_VECTOR(24 DOWNTO 0); SIGNAL P : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN P1:PROCESS (CP) Begin IF CP'Event AND CP='1' then Q <= Q+1; END IF; END PROCESS P1; P2:PROCESS (Q) Begin --NUM <= Q(24 DOWNTO 21);--about 1 Hz --P<= Q(24 DOWNTO 21); --S <= Q(15 DOWNTO 13);--about 300 Hz NUM <= Q(6 DOWNTO 3); S <= Q(1 DOWNTO 0); P<= Q(6 DOWNTO 3); END PROCESS P2; P3:PROCESS( S ) BEGIN CASE S IS WHEN "000" => SEL <= "000" ; WHEN "001" => SEL <= "001" ; WHEN "010" => SEL <= "010" ; WHEN "011" => SEL <= "011" ; WHEN "100" => SEL <= "100" ; WHEN "101" => SEL <= "101" ; WHEN "110" => SEL <= "110" ; WHEN "

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