用VHDL编程实现一个器件的功能

用VHDL编程实现一个器件的功能

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY qijian IS
PORT
(
a : IN std_logic_vector(0 to 2);--5=101b
b : IN std_logic_vector(0 to 2);
RST : IN STD_LOGIC;
CLK : IN STD_LOGIC;
EN : IN STD_LOGIC;
T : IN STD_LOGIC;
Y0 : OUT std_logic_vector(0 to 7);
Y1 : OUT std_logic_vector(0 to 7)
);
END qijian;

ARCHITECTURE a OF qijian IS
-- SIGNAL __count_signal_name : INTEGER RANGE 0 TO __count_value;
signal temp_Y0 : std_logic_vector(0 to 5);
signal temp_Y1 : std_logic_vector(0 to 3);
BEGIN
PROCESS (CLK, RST,EN,T)
BEGIN
if(CLK'event and clk = '1') then
IF RST = '1' THEN
temp_Y0 <= "000000";
temp_Y1 <= "0000";

ELSIF(EN = '1') THEN

IF T = '0' THEN

temp_Y0 <= a*a-b;

ELSE

temp_Y1 <= b & '0';

END IF;

END IF;

end if;
END PROCESS;
Y0 <="00" & temp_Y0;
Y1 <="0000" & temp_Y1;
END a;
a、b的数字范围为0到5，二进制就是000-101，所以定义为std_logic_vector(0 to 2)；
Y0=a*a-b,就会有6位数，所以temp_Y0 定义为std_logic_vector(0 to 5)；
Y1是b的四位数的循环左移，还是4位数，所以temp_Y1 为std_logic_vector(0 to 3);

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