vhdl程序设计1个4位加减法器

vhdl程序设计1个4位加减法器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity subadd4 is
port(sub:in std_logic;
a,b:in std_logic_vector(3 downto 0);
s:buffer std_logic_vector(3 downto 0);
co:buffer std_logic);
end entity subadd4;
architecture behav of subadd4 is
signal temp:std_logic_vector(4 downto 0);
begin
process(sub,a,b)
begin
if sub='0' then
temp(4 downto 0)<=('0'&a)+('0'&b);
else
temp(4 downto 0)<=('0'&a)-('0'&b);
end if;
end process;
s<=temp(3 downto 0);
co<=temp(4);
end behav;

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