用Verilog编写32位ALU
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解决时间 2021-11-20 19:16
- 提问者网友：一抹荒凉废墟
- 2021-11-19 18:37
用Verilog编写32位ALU
最佳答案
- 五星知识达人网友：夜风逐马
- 2021-11-19 19:58
哈哈，我写过
module ALU(sa,sb,ALUop,o);
input [31:0]sa,sb;
input [2:0]ALUop;
output [31:0]o;
reg [31:0]ol;
always@(sa or sb or ALUop)
begin
case(ALUop)
1:o=sa+sb;
2:o=sa-sb;
3:o=sa|sb;
4:{o,ol}=sa*sb;
5:o=sa/sb;
6:o=sa%sb;
endcase
end
endmodule
根据ALUop的不同，可以实现加、减、或、乘、除、取模运算，你也可以在此基础上增加其他运算。
module ALU(sa,sb,ALUop,o);
input [31:0]sa,sb;
input [2:0]ALUop;
output [31:0]o;
reg [31:0]ol;
always@(sa or sb or ALUop)
begin
case(ALUop)
1:o=sa+sb;
2:o=sa-sb;
3:o=sa|sb;
4:{o,ol}=sa*sb;
5:o=sa/sb;
6:o=sa%sb;
endcase
end
endmodule
根据ALUop的不同，可以实现加、减、或、乘、除、取模运算，你也可以在此基础上增加其他运算。
全部回答
- 1楼网友：梦中风几里
- 2021-11-19 21:13
ALU要有什么功能？加减乘除都要自己写还是直接用＋－*/就行了？
`timescale 1ns / 1ps
`include "def.v"
module ALU(a,b,f,s
);
parameter N=32;
input [N-1:0] a, b;
input [4:0] f;
output [N-1:0] s;
reg [N-1:0] s;
wire [N-1:0] x, y;
assign x = a + 32'h80000000;
assign y = b + 32'h80000000;
always @(a or b or x or y or f)
case(f)
`ADD : s = b + a;
`SUB : s = b - a;
`MUL : s = b * a;
`SHL : s = b << a;
`SHR : s = b >> a;
`BAND: s = b & a;
`BOR : s = b | a;
`BXOR: s = b ^ a;
`AND : s = b && a;
`OR : s = b || a;
`EQ : s = b == a;
`NE : s = b != a;
`GE : s = y >= x;
`LE : s = y <= x;
`GT : s = y > x;
`LT : s = y < x;
`NEG : s = -a;
`BNOT : s = ~a;
`NOT : s = !a;
default : s = 32'hxxxxxxxx;
endcase
endmodule
`timescale 1ns / 1ps
`include "def.v"
module ALU(a,b,f,s
);
parameter N=32;
input [N-1:0] a, b;
input [4:0] f;
output [N-1:0] s;
reg [N-1:0] s;
wire [N-1:0] x, y;
assign x = a + 32'h80000000;
assign y = b + 32'h80000000;
always @(a or b or x or y or f)
case(f)
`ADD : s = b + a;
`SUB : s = b - a;
`MUL : s = b * a;
`SHL : s = b << a;
`SHR : s = b >> a;
`BAND: s = b & a;
`BOR : s = b | a;
`BXOR: s = b ^ a;
`AND : s = b && a;
`OR : s = b || a;
`EQ : s = b == a;
`NE : s = b != a;
`GE : s = y >= x;
`LE : s = y <= x;
`GT : s = y > x;
`LT : s = y < x;
`NEG : s = -a;
`BNOT : s = ~a;
`NOT : s = !a;
default : s = 32'hxxxxxxxx;
endcase
endmodule
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