急求彩灯变换控制器设计 Verilog程序

急求彩灯变换控制器设计 Verilog程序

我做了下 但是没有编译 中间LED输出的逻辑还有点没做完 明天继续做吧

module LIGHT_CTRL(
clk , //sys clk 24mhz
rst_n , //n_reset

rst , //rst key

spd_set , //speed set

led_out , //LED output
state_out //STATE output
);

//Input PIN
input clk ; //sys clk 24mhz
input rst_n ; //n_reset

input rst ; //rst key
input [1:0] spd_set ; //speed set
//00:very fast 500 ms
//01: fast 1 s
//10: slow 2 s
//11:very slow 4 s

//Output PIN
output [7:0] led_out ; //LED output LED7~LED0
output [1:0] state_out ; //STATE output
//00:S0
//01:S1
//10:S2
//11:S3

//Register And Wire
//500ms pulse
wire n_500ms_pls ;
reg [31:0] r_cnt ;

//spd latch
reg [1:0] r_spd_set ;

//sec cnt
wire n_led_inc ;
reg [1:0] r_sec_cnt ;

//ctrl level
wire n_rst_pls ;
reg r_rst ;
reg r_sys_on ;

//led cnt
reg [3:0] r_led_cnt ;

//light ctrl state
wire n_state_end ;
reg [1:0] r_state ;

//led output
wire [7:0] n_led ;
reg [7:0] led_out ;
reg [1:0] state_out ;

//***RTL***
//500ms pulse
assign n_500ms_pls = (r_cnt == 32'h00B7_1AFF)? 1'b1 : 1'b0; //when cnt=11999999,500ms pulse

always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
r_cnt <= 32'h0000_0000;
end
else begin
if(r_sys_on == 1'b1)
if(n_500ms_pls == 1'b1)
r_cnt <= 32'h0000_0000;
else
r_cnt <= r_cnt + 1'b1;
else
r_cnt <= 32'h0000_0000;
end
end

//spd latch
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
r_spd_set <= 2'b10;
end
else begin
if(n_rst_pls == 1'b1)
r_spd_set <= 2'b10;
else if((n_led_inc == 1'b1) && (n_state_end == 1'b1))
r_spd_set <= spd_set;
else
r_spd_set <= r_spd_set;
end
end

//sec cnt
assign n_led_inc = (n_500ms_pls == 1'b0) ? 1'b0 :
(r_sec_cnt == r_spd_set) ? 1'b1 : 1'b0;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
r_sec_cnt <= 2'b00;
end
else begin
if(r_sys_on == 1'b1)
if(n_500ms_pls == 1'b1)
if(r_sec_cnt == r_spd_set)
r_sec_cnt <= 2'b00;
else
r_sec_cnt <= r_sec_cnt + 1'b1;
else
r_sec_cnt <= r_sec_cnt;
else
r_sec_cnt <= 2'b00;
end
end

//ctrl level
assign n_rst_pls = rst & ~r_rst;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
r_rst <= 1'b0;
end
else begin
r_rst <= rst;
end
end

always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
r_sys_on <= 1'b0;
end
else begin
if(n_rst_pls == 1'b1)
r_sys_on <= ~r_sys_on;
else
r_sys_on <= r_sys_on;
end
end

//led cnt
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
r_led_cnt <= 4'h0;
end
else begin
if(r_sys_on == 1'b1)
if(n_led_inc == 1'b1)
if(n_state_end == 1'b1)
r_led_cnt <= 4'h0;
else
r_led_cnt <= r_led_cnt + 1'b0;
else
r_led_cnt <= r_led_cnt;
else
r_led_cnt <= 4'h0;
end
end

//light ctrl state
assign n_state_end = ((r_state[1:0] == 2'b00) && (r_led_cnt == 4'b1000)) &
((r_state[1:0] == 2'b01) && (r_led_cnt == 4'b1000)) &
((r_state[1:0] == 2'b10) && (r_led_cnt == 4'b0100)) &
((r_state[1:0] == 2'b11) && (r_led_cnt == 4'b0100)) ;

always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
r_state <= 2'b00;
end
else begin
if(r_sys_on == 1'b1)
if(n_led_inc == 1'b1)
if(n_state_end == 1'b1)
r_state <= r_state + 1'b1;
else
r_state <= r_state;
else
r_state <= r_state;
else
r_state <= 2'b00;
end
end

//led output
assign n_led[7] = ((r_state[1:0] == 2'b00) && (r_led_cnt[3] | r_led_cnt[2] | r_led_cnt[1] | r_led_cnt[0] )) || //OXXX_XXXX
((r_state[1:0] == 2'b01) && (r_led_cnt[3] )) || //O..._....
((r_state[1:0] == 2'b10) && ( r_led_cnt[2] | r_led_cnt[1] | r_led_cnt[0] )) || //OXXX_XXXO
((r_state[1:0] == 2'b11) && ( r_led_cnt[2] )) || //O..._...O

assign n_led[6] = ((r_state[1:0] == 2'b00) && (r_led_cnt[3] | r_led_cnt[2] | r_led_cnt[1] )) || //.OXX_XXXX
((r_state[1:0] == 2'b01) && (r_led_cnt[3] | (r_led_cnt[2] & r_led_cnt[1] & r_led_cnt[0]))) || //XO.._....
((r_state[1:0] == 2'b10) && ( r_led_cnt[2] | r_led_cnt[1] )) || //.OXX_XXO.
((r_state[1:0] == 2'b11) && ( r_led_cnt[2] | (r_led_cnt[1] & r_led_cnt[0]))) || //XO.._..OX

assign n_led[5] = ((r_state[1:0] == 2'b00) && (r_led_cnt[3] | r_led_cnt[2] | (r_led_cnt[1] & r_led_cnt[0]))) || //..OX_XXXX
((r_state[1:0] == 2'b01) && (r_led_cnt[3] | (r_led_cnt[2] & r_led_cnt[1] ))) || //XXO._....
((r_state[1:0] == 2'b10) && ( r_led_cnt[2] | (r_led_cnt[1] & r_led_cnt[0]))) || //..OX_XO..
((r_state[1:0] == 2'b11) && ( r_led_cnt[2] | r_led_cnt[1] )) || //XXO._.OXX

assign n_led[4] = ((r_state[1:0] == 2'b00) && (r_led_cnt[3] | r_led_cnt[2] | (r_led_cnt[1] & r_led_cnt[0]))) || //..OX_XXXX
((r_state[1:0] == 2'b01) && (r_led_cnt[3] | (r_led_cnt[2] & r_led_cnt[1] ))) || //XXO._....
((r_state[1:0] == 2'b10) && ( r_led_cnt[2] | (r_led_cnt[1] & r_led_cnt[0]))) || //..OX_XO..
((r_state[1:0] == 2'b11) && ( r_led_cnt[2] | r_led_cnt[1] )) || //XXO._.OXX

........................

//light blink ctrl
//0:Off;1:On;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
led_out <= 8'b0000_0000;
state_out <= 2'b00;
end
else begin
led_out <= n_led;
state_out <= r_state;
end
end

endmodule追问先谢谢你了!你简直是我的救命恩人

注释能不能用中文写一下，有些看不太懂，最好仿真一下完了吧波形也给我截一下追答输入时钟24MHz
reset输入信号 rst_n
rst启动信号 按一下启动再按一下关掉
spd_set输入信号是LED点亮速度控制 2bit
00:very fast 500 ms
01: fast 1 s
10: slow 2 s
11:very slow 4 s

输出led_out LED7是最左边的 LED0是最右边的
输出state_out 状态输出 2bit
00:S0
01:S1
10:S2
11:S3追问4档快、稍快、中速、慢速，默认工作为中速。这个怎么做，什么原理追答两个counter 一个计时500ms 另一个计时0，1，2，4（也就是500ms,1s,2s,4s）

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